Liquid crystal displays have been used widely in various fields of manufacturing and living, and display is implemented in a liquid crystal display by using driving circuits to drive respective pixels in a liquid crystal panel. Driving circuits of a liquid crystal display majorly comprise a gate driving circuit and a data driving circuit, wherein the data driving circuit is used to latch input image data in accordance with timings of a clock signal and convert the latched data into analog signals so as to input the same to data lines of the liquid crystal panel, and the gate driving circuit is used to convert the clock signal into a turn-on/turn-off voltage through a shift register (SR) and output the same to a corresponding gate line of the liquid crystal panel. Wherein only a current stage of shift register outputs the turn-on voltage at a same time, that is to say, only the voltage on the gate line corresponding to one row of pixels is the turn-on voltage, and voltages on the gate lines corresponding to remaining rows of pixels are all the turn-off voltage, so that the data signal at this moment is only input to the row of pixels through the data driving circuit. At a next moment, a next stage of shift register outputs a scanning signal so that the voltage on the gate line corresponding to a next row of pixels is the turn-on voltage, and the voltages on the gate lines corresponding to remaining rows of pixels are all the turn-off voltage. The rest may be deduced similarly, and a progressive scanning of the pixels in the liquid crystal panel may be achieved. The above turn-on voltage occurs on the respective rows sequentially and progressively and is also referred to as a scanning signal.
In the structure described above, the main method for converting the clock signal into the scanning signal by the shift register is to trigger an operation of a current stage of shift register in response to the output of the scanning signal from a previous stage of shift register, and then output the clock signal of the current stage of shift register as the scanning signal, and at the same time, the scanning signal at the current stage is fed back to the previous stage of shift register on one hand so as to reset the previous stage of shift register, and is input to the next stage of shift register as a shift trigging signal for the next stage of shift register on the other hand. Similarly, the respective stages of shift registers output the scanning signal sequentially.
However, as well-known by those skilled in the art, the clock signal is a square wave which is switched periodically between a first level and a second level, and there are many clock cycles in a scanning period during which the scanning signal cycles from a first row of pixels to a last row of pixels. With respect to a certain shift register, only a time period being half of the clock cycle is used to output the scanning signal, but the output terminal of the shift register may generally output a fluctuated level under an effect of the clock signal in remaining clock cycles during which no scanning signal should be output, such that a great circuit noise occurs on the corresponding gate line and the thin film transistors in the pixel units may be turned on improperly, and in turn the circuit functions abnormally.